12 J-BERT N4903A High-Performance Serial BERT Data Sheet
Table 16: Specifications for trigger output
Clock divider 4, 8, 16 up to 11 Gb/s
32, 40, 64, 128 up to 12.5 Gb/s
Levels High: +0.5 V typical
Low: --0.5 V typical
Minimum pulse width Pattern length x clock period/2
e.g. 10 Gb/s with 1000 bits = 50ns
Interface DC coupled, 50 W nominal
Connector SMA female
Table 18: Specifications for the auxiliary output
Amplitude 600 mV typical
Interface AC coupled, 50 W nominal
Connector SMA female
Table 19: Specifications for gating input
Burst synchronization time 1536 bits for PRBS
15 kbit for pattern
Backlash 1536 bits in non-CDR mode
1.5 µs in CDR-mode
Gate passive time 2560 bits in non-CDR mode
2560 bits or 1.5 µs whichever
is longer, in CDR-mode
Interface levels TTL levels
Pulse width 256 clock periods
Connector SMA female
Table 17: Specifications for error output
Interface format RZ, active high
Levels High: 1 V typical
Low: 0 V typical
Pulse width 128 clock periods
Interface DC coupled, 50 W nominal
Connector SMA female
Trigger output (TRIG OUT)
Pattern trigger mode
This provides a trigger synchronized with the
selected error detector reference pattern. In pat-
tern mode the pulse is synchronized to repetitions
of the output pattern. It generates 1 pulse for every
4th PRBS pattern.
Divided clock mode
In divided clock mode, the trigger is a square wave.
Error output (ERR OUT)
This provides a signal to indicate received errors.
The output is the logical 'OR' of errors in a 128 bit
segment of the data.
Auxiliary output (AUX OUT)
This output can be used to provide either clock or
data signals:
Clock: clock signals from the input or the recov-
ered clock signals in CDR mode.
Data: weighted and sampled data.
Gating input (GATE IN)
If a logical high is applied to the gating input the
analyzer will ignore the incoming bits during a
BER measurement. The ignored bit sequence is a
multiple of 512 bits. For measuring data in bursts
of bits, rather than a continuous stream of bits, a
special operating mode is used. This is the burst
sync mode. In this case, the signal at the gating
input controls the synchronization and the error
counting for each burst.
This is an important feature for recirculation loop
measurements. If clock data recovery (CDR) is
used to recover the clock from the burst data, the
CDR takes 2 µs from the start of the burst data to
settle. The number of bits needed to synchronize
itself during a burst depends on whether the pat-
tern consists of hardware based PRBS data or
memory based data. To run properly in burst mode
the system needs a backlash of data after the gat-
ing input returns to high. During each burst, the
gating input has to remain passive.
Figure 20: Burst mode allows recirculation loop testing.
Pattern capture
The error detector can capture up to 32 MB data
bits from the device under test. The captured data
bits are displayed in the pattern editor in hex or
binary format. The data bits can be used as
expected data for BER testing or can be saved for
post processing.
Specifications-Error Detector
(482 paginas)
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