Agilent Technologies HP 3325B Especificaciones

Printed in USA July 2004NoticeHewlett-Packard to Agilent Technologies TransitionThis manual may contain references to HP or Hewlett-Packard. Please no

To return assemblies 6–187 Replaceable PartsReplaceable Parts Ordering 7–2Replaceable Parts List 7–3Exploded View 7–4Power Cables and Plug Configu

To test the input resistance (oscilloscope)Testing the input resistance verifies the performance of the following specification:• Input resistanceThis

Set up the logic analyzer1 Set up the Channel menu.a Press the Config key.b At the pop up menu, select Scope Channel.c Select the Input field, then se

Connect the logic analyzerUsing the BNC-to-banana adapters, connect one end of each BNC cable to the 4-wireresistance connections on the multimeter, a

Acquire the data1 Press the RUN key. The clicking of attenuator relays should be audible. Verifyresistance readings on the digital multimeter of 50

To test the voltage measurement accuracy (oscilloscope)Testing the voltage measurement accuracy verifies the performance of the followingspecification

Set up the logic analyzer1 Set up the Channel menu.a Press the Config key. In the pop up menu, select Scope Channel.b Select the Input field, then se

4 Set up the Marker menu.a Press the Marker key.b Move the cursor to the V Markers field and press Select. The voltage markers shouldnow be On.c Sele

Acquire the dataUse the following table for steps 1 through 5. Oscilloscope Settings Voltage ReadingsV/Div Offset Supply Upper Limit Lower Limit

To test the offset accuracy (oscilloscope)Testing the offset accuracy verifies the performance of the following specification:• Offset accuracyEquipme

Set up the logic analyzer1 Set up the Configuration menu.a Press the Config key. At the pop up menu, select Scope Channel.b Select the Input field, t

x

3 Set up the Trigger menu.a Press the Trigger key.b Select the Mode/Arm field, then select Immediate.4Set up the Marker menu.a Press the Marker key.b

Acquire the zero input data1 Disconnect the power supply from the channel input.2 Press the Chan key. Move the cursor to the V/Div field and press th

Acquire the DC input dataUse the following table for steps 1 through 5.Multimeter SettingsScope Settings Power SupplySettingsScope ReadingsV/Div Offse

To test the bandwidth (oscilloscope)Testing the bandwidth verifies the performance of the following specification:• BandwidthThis test verifies the ba

Set up the logic analyzer1 Set up the Configuration menu.a Press the Config key. At the pop up menu, select Scope Channel.b Select the Input field, t

3 Set up the Trigger menu.a Press the Trigger key.b Select the Mode/Arm field, then select Edge.c Select the Source field, then select C1.d Move the c

Connect the logic analyzer1 Using the N cable, connect the signal generator to the power splitter input. Connectthe power sensor to one output of the

Acquire the data1 Obtain the 1 MHz response.aSet the signal generator for 1 MHz at −2.4 dBm. b Press the blue shift key, then press the Run key. The

To test the time measurement accuracy (oscilloscope)Testing the time measurement accuracy verifies the performance of the followingspecification:• Tim

Set up the logic analyzer11 Set up the Configuration menu.a Press the Config key. At the pop up menu, select Scope Channel.b Select the Input field,

1Accessories 1–2Specifications (logic analyzer) 1–3Specifications (oscilloscope) 1–4Specifications (pattern generator) 1–4Characteristics (logic

3 Set up the Trigger menu.a Press the Trigger key.b Select the Mode/Arm field, then select Edge.c Select the Source field and set it to C1.d Move the

Connect the logic analyzerUsing the N-to-BNC adapter and the BNC cable, connect the signal generator outputto the channel 1 input of the oscilloscope.

To test the trigger sensitivity (oscilloscope)Testing the trigger sensitivity verifies the performance of the following specifications:• DC to 50 MHz:

Set up the logic analyzer11 Set up the Configuration menu.a Press the Config key. At the pop up menu, select Scope Channel.b Select the Input field, t

3 Set up the Trigger menu.a Press the Trigger key.b Select the Mode/Arm field, then select Edge.c Select the Source field and set it to C1.d Move the

Connect the logic analyzerUsing the N-to-BNC adapter and the BNC cable, connect the signal generator outputto the channel 1 input of the oscilloscope.

Performance Test Record (logic analyzer)Performance Test Record (logic analyzer)HP 1660C/CS/CP-Series LogicAnalyzer_______Serial No.__________________

Performance Test Record (continued)Test Settings ResultsThreshold Accuracy (cont)Limits MeasuredPod 4 TTL, ±145 mVECL, ±139 mV-User, ±280 mV+User, ±2

Performance Test Record (continued)Test Settings ResultsGlitch CaptureMinimum DetectableGlitch 3.5 nsPass/FailPod 1 ________Pod 2 ________Pod 3 ______

Performance Test Record (continued)Test Settings ResultsSingle-Clock,Single-EdgeAcquisitionPass/Fail Pass/FailAll Pods, Channel 3 Setup/Hold Time 3.5

General InformationThis chapter lists the accessories, the specifications and characteristics, and therecommended test equipment.Accessories The follo

Performance Test Record (continued)Test Settings ResultsMultiple-Clock,Multiple-EdgeAcquisitionEnable pulse generator, channel 2COMP (LED on)Disable p

Performance Test Record (continued)Test Settings ResultsSingle-Clock,Multiple-EdgeAcquisitionDisable pulse generator, channel 1 COMP (LED off)Pass/Fai

Performance Test Record (oscilloscope)Performance Test Record (oscilloscope)Test Settings ResultsSelf-TestsPass/Fail ________DC CAL OutputAC CAL Outpu

Performance Test Record (oscilloscope)Test Settings ResultsVoltageMeasurementAccuracyChannel 1 Channel 2 Zero InputZero InputLimits-13.7 V to -14.3 V-

Performance Test Record (oscilloscope)Test Settings ResultsBandwidthChannel 1Channel 2Limit ≤−3.0 dB ≤−3.0 dBMeasured________________TimeMeasurementAc

Performance Test Record (pattern generator)Performance Test Record (pattern generator)Test Settings ResultsSelf-TestsPass/Fail ________3–104

4Logic analyzer calibration 4–2To calibrate the oscilloscope 4–3Set up the equipment 4–3Load the Default Calibration Factors 4–4Self Cal menu cali

Calibrating and AdjustingThis chapter gives you instructions for calibrating and adjusting the logic analyzer.Adjustments to the logic analyzer includ

To calibrate the oscilloscopeEquipment RequiredEquipment Critical Specification RecommendedModel/PartQtyCable (2) BNC, 9-inch (equal length) HP 10502A

Load the Default Calibration FactorsNote that once the default calibration factors are loaded, all calibrations must bedone. This includes all of the

Specifications (logic analyzer)The specifications are the performance standards against which the product is tested.Maximum State Speed 100 MHzMinimum

Self Cal menu calibrationsMessages will be displayed as each calibration routine is completed to indicate calibration haspassed or failed. The result

To adjust the CRT monitor alignmentThis procedure must be performed by trained personnel. Adjustments are made withthe cover removed and power applie

4 Enter the Sys PV tests, then enter the Display Test. A grid pattern should appear.5If the display is tilted (rotated), adjust the CRT yoke by rotati

To adjust the CRT intensityThis procedure must be performed by trained personnel. Adjustments are made withthe cover removed and power applied.WARNIN

WARNINGDo not touch the CRT monitor sweep board. High voltages exist on the sweep board that cancause personal injury.7The light power meter should r

4–10

5To use the flowcharts 5–2To check the power-up tests 5–17To run the self-tests 5–18To test the power supply voltages 5–24To test the CRT monitor

TroubleshootingThis chapter helps you troubleshoot the logic analyzer to find defective assemblies.The troubleshooting consists of flowcharts, self-te

Troubleshooting Flowchart 1TroubleshootingTo use the flowcharts5–3

Troubleshooting Flowchart 2TroubleshootingTo use the flowcharts5–4

Specifications (oscilloscope)The HP 1660CS Logic Analyzers also include the following specifications:Bandwidth (*,1)DC to 250 MHz (real time, dc-coupl

Troubleshooting Flowchart 3TroubleshootingTo use the flowcharts5–5

Troubleshooting Flowchart 4TroubleshootingTo use the flowcharts5–6

Troubleshooting Flowchart 5TroubleshootingTo use the flowcharts5–7

Troubleshooting Flowchart 6TroubleshootingTo use the flowcharts5–8

Troubleshooting Flowchart 7TroubleshootingTo use the flowcharts5–9

Troubleshooting Flowchart 8TroubleshootingTo use the flowcharts5–10

Troubleshooting Flowchart 9TroubleshootingTo use the flowcharts5–11

Troubleshooting Flowchart 10TroubleshootingTo use the flowcharts5–12

Troubleshooting Flowchart 11TroubleshootingTo use the flowcharts5–13

Troubleshooting Flowchart 12TroubleshootingTo use the flowcharts5–14

Characteristics (logic analyzer)These characteristics are not specifications, but are included as additional information.Full Channel Half ChannelMaxi

Troubleshooting Flowchart 13TroubleshootingTo use the flowcharts5–15

Troubleshooting Flowchart 14TroubleshootingTo use the flowcharts5–16

To check the power-up testsThe logic analyzer automatically performs power-up tests when you apply power to theinstrument. The revision number of the

To run the self-testsSelf-tests identify the correct operation of major functional areas of the instrument. You canrun all self-tests without accessi

5 Select ROM Test. The ROM Test screen is displayed.You can run all tests at one time by running All System Tests. To see more details about eachte

7 To exit the ROM Test, select Done. Note that the status changes to Passed or Failed.8 Install a formatted disk that is not write protected into the

11 Select Sys PV, then select Analy PV in the pop-up menu. Select Chip 2 Tests.You can run all the analyzer tests at one time by selecting All Analyz

13 Select Board Tests, then select Run. When the Board Tests are finished, select Done.14 Select Data Input Inspection. All lines should show activi

17 In the Data Memory Test menu, select Run, then select Single. The test runs onetime, then the screen shows the results. When the test is finished

To test the power supply voltagesTo check the voltages, the power supply must be loaded by either the acquisition board orwith an added resistor.Refer

Characteristics (pattern generator)The HP 1660CP Logic Analyzers also include the following characteristics:Output channels 16 channels at 200 MHz clo

6 Check for the voltages on the power supply cable using the values in the followingtable.Signals on the Power Supply CablePin Signal Pin Signal1 +5.0

To test the CRT monitor signalsRefer to chapter 6, "Replacing Assemblies," for instructions to remove or replace covers andassemblies.WARNIN

To test the keyboard signalsRefer to chapter 6, "Replacing Assemblies," for instructions to remove covers and assemblies.WARNINGHazard volta

To test the flexible disk drive voltagesRefer to chapter 6, "Replacing Assemblies," for instructions to remove or replace covers andassembli

6 Check for the following voltages and signals using an oscilloscope.Disk Drive VoltagesPin Signal Description Pin Signal Description1 NC 2 Disk Chang

To test the hard disk drive voltagesRefer to chapter 6, "Replacing Assemblies," for instructions to remove or replace covers andassemblies.W

The test will not immediately stop when Stop is selected; it will continue until the currentiteration of the disk test is completed and then stop.7 Di

To test the logic analyzer probe cablesThis test allows you to functionally verify the probe cable and probe tip assembly of any of thelogic analyzer

4 Set up the Format menu.a Press the Format key.b Move the cursor to the field showing the channel assignments for the pod under test.Press the Clear

e Select the field to the right of the pod being tested, then select TTL.5Set up the Trigger menu.a Press the Trigger key.b Select Modify Trigger, the

Supplemental Characteristics (logic analyzer)ProbesInput Resistance 100 kΩ, ± 2%Input Capacitance ~ 8 pFMinimum Voltage Swing 500 mV, peak-to-peakThre

7 Using four 6-by-2 test connectors, four BNC Couplers, and four SMA (m) - BNC (f)Adapters, connect the logic analyzer to the pulse generator channel

To verify pattern output (HP 1660CP-Series only)Equipment RequiredEquipment Critical Specification Recommended Model/PartOscilloscope ≥ 500 MHz Bandwi

4 Repeat step 3 for each of the remaining four data pods.5 Connect one of the 10460-series clock pods to the end of the pattern generator clockcable.6

To test the auxiliary powerThe +5 V auxiliary power is protected by a current overload protection device. If the currenton pins 1 and 39 exceed 0.33

6To remove and replace theHandle 6–5Feet and tilt stand 6–5Cover 6–5Disk drive assembly 6–6Power supply 6–7CPU board 6–7SIMM memory 6–8Switch act

Replacing AssembliesThis chapter contains the instructions for removing and replacing the assemblies ofthe logic analyzer. Also in this chapter are in

Exploded ViewListingA1 Keyboard MP1 Intensity adjustment W1 HP-IB cableA2 CPU board MP2 Disk drive bracket W2 Fan cableA3 I/O Board MP3 Fan guard W3 R

Exploded View of the HP 1660CReplacing Assemblies6–4

To remove and replace the handle• Remove the two screws in the endcaps, then lift off the handle.To remove and replace the feet and tilt stand1 Remove

To remove and replace the disk drive assembly1 Using previous procedures, remove the following assemblies:•Handle•Rear Feet•Cover2Disconnect the two d

Measurement and Display FunctionsDisplayed Waveforms 24 lines maximum, with scrolling across 96 waveforms.Measurement FunctionsRun/Stop Functions Run

To remove and replace the power supply1 Using previous procedures, remove the following assemblies:•Handle•Rear Feet•Cover•Disk Drive AssemblyWARNINGH

To remove and replace SIMM memory1 Using previous procedures, remove the following assemblies:•Handle•Rear Feet•Cover•Disk Drive Assembly•Power Supply

To remove and replace the switch actuator assembly1 Using previous procedures, remove the following assemblies:•Handle•Rear Feet•Cover•Disk Drive Asse

To remove and replace the rear panel assembly1 Using previous procedures, remove the following assemblies:•Handle•Rear Feet•Cover•Disk Drive Assembly•

To remove and replace the HP 1660C-series acquisition board1 Using previous procedures, remove the following assemblies:•Handle•Rear Feet•Cover•Rear P

To remove and replace the HP 1660CS-series oscilloscope board1 Using previous procedures, remove the following assemblies:•Handle•Rear Feet•Cover•Rear

To remove and replace the HP 1660CP-series pattern generatorboard1 Using previous procedures, remove the following assemblies:•Handle•Rear Feet•Cover•

To remove and replace the front panel and keyboard1 Using previous procedures, remove the following assemblies:•Handle•Rear Feet•Cover•Disk Drive Asse

To remove and replace the monitor1 Using previous procedures, remove the following assemblies:•Handle•Rear Feet•Cover•Disk Drive Assembly•Power Supply

To remove and replace the fan1 Using previous procedures, remove the following assemblies:•Handle•Rear Feet•Cover•Disk Drive Assembly•Power Supply•Rea

Service GuidePublication number 01660-97026First edition, November 1997For Safety information, Warranties, and Regulatoryinformation, see the pages at

Marker FunctionsTime Interval The X and O markers measure the time interval between a point on atiming waveform and the trigger, two points on the sam

To remove and replace the HP 1660CP-series pattern generatorcables1 Using previous procedures, remove the following assemblies:•Handle•Rear Feet•Cover

To remove and replace the I/O board1 Using previous procedures, remove the following assemblies:•Handle•Rear Feet•Cover•Disk Drive Assembly•Power Supp

7Replaceable Parts Ordering 7–2Replaceable Parts List 7–3Exploded View 7–4Power Cables and Plug Configurations 7–8Replaceable Parts

Replaceable PartsThis chapter contains information for identifying and ordering replaceable parts foryour logic analyzer.Replaceable Parts OrderingPar

Replaceable Parts ListThe replaceable parts list is organized by reference designation and shows exchangeassemblies, electrical assemblies, then other

Exploded ViewExploded view of the HP 1660 logic analyzer.Replaceable PartsExploded View7–4

HP 1660 Series Replaceable PartsRef.Des.HP PartNumber QTY DescriptionExchange Board Assembly01660-69528 Exchange Board Assembly - CPU01660-69517 Excha

HP 1660 Series Replaceable PartsRef.Des.HP PartNumber QTY DescriptionH13 0515-1103 2 MSFH M3 10 T10 (trim strip cover to cabinet)H14 0515-0664 4 MSPH

HP 1660 Series Replaceable PartsRef.Des.HP PartNumber QTY DescriptionMP29 01660-44703 1 Front panel spacerMP30 01660-44702 1 Keyboard spacerMP33 01660

Power Cables and Plug ConfigurationsThis instrument is equipped with a three-wire power cable. The type of power cable plugshipped with the instrumen

Product RegulationsSafety IEC 1010-1:1990+A1 / EN 61010-1:1993UL3111CSA-C22.2 No. 1010.1:1993EMC This product meets the requirement of the EuropeanCom

8Block-Level Theory 8–3The HP 1660C/CS/CP Series Logic Analyzer 8–3The Logic Acquisition Board 8–7The Oscilloscope Board 8–10The Pattern Generator

Theory of OperationThis chapter tells the theory of operation for the logic analyzer and describes theself-tests. The information in this chapter is

Block-Level TheoryThe block-level theory is divided into two parts: theory for the logic analyzer andtheory for the acquisition boards. A block diagr

HP 1660C/CS/CP Series TheoryCPU BoardThe microprocessor is a Motorola 68EC020 running at 25 MHz. The microprocessor controlsall of the functions of th

HP-IB InterfaceThe instrument interfaces to HP-IB as defined by IEEE Standard 488.2. The interfaceconsists of an HP-IB controller and two octal drive

Keyboard/Mouse InterfaceAn 82C42PC PS2 controller makes up the PS2 Keyboard/Mouse interface. The PS2 controllerinterfaces the logic analyzer backplane

The Logic Acquisition BoardThe Logic Acquisition BoardTheory of OperationThe Logic Acquisition Board8–7

Logic Acquisition Board TheoryProbingThe probing circuit includes the probe cable and terminations. The probe cable consists oftwo 17-channel pods wh

Clock optimization involves using programmable delays on board the IC to position the masterclock transition where valid data is captured. This proce

The Oscilloscope BoardThe Oscilloscope BoardTheory of OperationThe Oscilloscope Board8–10

TimebaseRange 1 ns/div to 5 s/divResolution 20 psDelay Pre-trigger RangeTime/div Setting Available Delay1 µs to 5 s/div -8 x (s/div)1 ns to 500 ns/di

Oscilloscope Board Theory (HP 1660CS series only)Attenuator/Preamp Theory of OperationThe channel signals are conditioned by the attenuator/preamps, t

Time Base The time base provides the sample clocks and timing necessary for dataacquisition. It consists of the 100 MHz reference oscillator and time

The Pattern Generator BoardThe Pattern Generator BoardPattern Generator Board Theory (HP 1660CP series only)Loop RegisterThe loop register holds the p

Output DriverThe output driver circuit is made up of a series of latch/logic translators and multiplexers. Thelatch/translators convert the working-le

Self-Tests DescriptionThe self-tests identify the correct operation of major functional areas in the logicanalyzer. The self-tests are not intended f

RAM TestThe RAM test checks the video RAM (VRAM), system dynamic RAM (DRAM), and static RAMmemory within the real time clock IC. The microprocessor f

HP-IB TestThe HP-IB test performs a write/read operation to each of the registers of the HP-IB IC. Atest pattern is written to each register in the H

Perform Test AllSelecting Perform Test All will initiate all of the previous functional verification tests in theorder they are listed. The failure o

Status BitsBit 0 The internal registers of the LAN IC are loaded with known test values and then are read. If this bit is not set, it implies thatthe

Analyzer Tests (Analy PV)The analyzer tests are functional performance verification tests. There are three types ofanalyzer tests: the Board Test, th

DigitizerResolution 8 bits (1 part in 256)Digitizing Rate Up to 1 Gigasample per secondDigitizing Technique Real-time digitizing; each 8000 samples ar

Resource Test The pattern, range, edge, and glitch recognizers are tested and verified.First, the test register is verified for correct operation. Ne

Oscilloscope tests (Scope PV)The following self-tests check the major components of the HP 1660CS-series oscilloscopeboard as well as all associated c

Pattern Generator tests (Patt Gen)The following section contains a description of each of the the pattern generator self tests. Clock Source TestThe C

Bits 6-13 contain the row of the page that failed.Bits 0-5 contain the failure code for the six RAM ICs on the board. Bits 0-4 contain the failurecod

Diagnostic Integer Value: This test is only valid for signals on the master board of theconfiguration. The values returned from any expansion cards wi

Subtest #3 — If Instruction Test This test checks the functionality of the if branching.Instruction memory is loaded with a wait on event ’a’ instruct

HP-IBThe Hewlett-Packard Interface bus (HP-IB) is Hewlett-Packard’s implementation ofIEEE Standard 488-1978, "Standard Digital Interface for Prog

RS-232-CThe logic analyzer interfaces with RS-232-C communication lines through a standard25 pin D connector. The logic analyzer is compatible with R

© Copyright Hewlett-Packard Company 1987 - 1997All Rights Reserved.Reproduction, adaptation, ortranslation without prior writtenpermission is prohibit

Product WarrantyThis Hewlett-Packard product hasa warranty against defects inmaterial and workmanship for aperiod of one year from date ofshipment. D

Measurement and Display FunctionsTime Markers Two vertical markers, X and O, are provided for measurements of timeand voltage. Capabilities are: meas

Recommended test equipment (logic analyzer)Equipment RequiredEquipment Critical Specifications RecommendedModel/PartUse*Pulse Generator 100 MHz, 3.5 n

Recommended test equipment (oscilloscope)Equipment RequiredEquipment Critical Specifications RecommendedModel/PartUse*Signal Generator Frequency: 1 -

Recommended test equipment (pattern generator)Equipment RequiredEquipment Critical Specifications RecommendedModel/PartUse*Oscilloscope ≥ 500 MHz Band

2To inspect the logic analyzer 2–2To apply power 2–3To operate the user interface 2–3To set the line voltage 2–3To degauss the display 2–4To clea

Preparing For UseThis chapter gives you instructions for preparing the logic analyzer for use. Power RequirementsThe logic analyzer power source requi

HP 1660C-Series, HP 1660CS-Series, and HP 1660CP-Series Logic AnalyzersThe HP 1660C-Series are 100-MHz State/500 MHz Timing Logic Analyzers.The HP 166

To apply power1 Check that the line voltage selector, located on the rear panel, is on the correctsetting and the correct fuse is installed.See also,

3 Reinsert the fuse module with the arrow for the appropriate line voltage alignedwith the arrow on the line filter assembly switch.4 Reconnect the po

3To perform the self-tests 3–3To make the test connectors (logic analyzer) 3–7To test the threshold accuracy (logic analyzer) 3–9To test the glitch

Testing PerformanceThis chapter tells you how to test the performance of the logic analyzer against thespecifications listed in chapter 1. To ensure

To perform the self-testsThe self-tests verify the correct operation of the logic analyzer. Self-tests can beperformed all at once or one at a time.

5 Install a formatted disk that is not write-protected into the disk drive. Connect anRS-232-C loopback connector onto the RS-232-C port.6 Select All

9 Select Sys PV, then select Analy PV in the pop-up menu. In the Analy PV menu,Select All Analyzer Tests. You can run all tests at one time, except f

13 For the HP 1660CS-series Logic Analyzers, Select Analy PV, then select Scope PV inthe pop-up menu. In the Scope PV menu, select Functional Tests t

To make the test connectors (logic analyzer)The test connectors connect the logic analyzer to the test equipment. The followingmaterials are required

2 Build one test connector using a BNC connector and a 17-by-2 section of Berg strip.a Solder a jumper wire to all pins on one side of the Berg strip.

The HP 1660CS-Series Logic Analyzers also include the following features:• 1 GSa/s digitizing for 250 MHz bandwidth single shot oscilloscope• 8000 sam

To test the threshold accuracy (logic analyzer)Testing the threshold accuracy verifies the performance of the following specification:• Clock and data

Set up the logic analyzer1 Press the Config key. 2 Unassign Pods 3 and 4, Pods 5 and 6, and Pods 7 and 8. To unassign the pods, selectthe pod field.

Test the TTL threshold1 Press the Format key. Select the field to the right of Pod A1, then select TTL in thepop-up menu.2On the function generator f

4 Using the Modify up arrow on the function generator, increase offset voltage in1-mV increments until all activity indicators for pod 1 show the chan

Test the ECL threshold1 Select the field to the right of Pod A1, then select ECL in the pop-up menu.2On the function generator front panel, enter −1.1

Test the − User threshold1 Move the cursor to the field to the right of Pod A1. Type –6.00, then use the left andright cursor control keys to highlig

Test the + User threshold1 Move the cursor to the field to the right of Pod A1. Type +6.00, then use the left andright cursor control keys to highlig

Test the 0 V User threshold1 Move the cursor to the field to the right of Pod A1. Type 0, then press the Select key.2On the function generator front

Test the next pod1 Using the 17-by-2 test connector and probe tip assembly, connect the data and clockchannels of the next pod to the output of the fu

To test the glitch capture (logic analyzer)Testing the glitch capture verifies the performance of the following specification:• Minimum detectable gli

In This BookThis book is the service guide for the HP 1660C/CS/CP-Series Logic Analyzers and is dividedinto eight chapters.Chapter 1 contains informat

3 Set up the oscilloscope. Oscilloscope SetupTime Base Display Delta V Delta T Time/Div: 1.00 ns/div mode: avg V markers on T markers ondelay: 17.700

The table includes all the HP 1660C/CS/CP Series. Use the pods that correspond toyour logic analyzer:•HP 1660C/CS/CP – pods 1 through 8•HP 1661C/CS/C

Test the glitch capture on the connected channels 1 Set up the Format menu.a Press the Format key.b Select the field to the right of each pod, then se

3 Set up the Trigger menu.a Press the Trigger key.b Select Modify Trigger, then select Clear Trigger, then select All.4Using the [Shift] + width: cha

6 On the logic analyzer, press the Run key. The display should be similar to the figurebelow. 7 On the pulse generator, enable Channel 1 and Channel

To test the single-clock, single-edge, state acquisition(logic analyzer)Testing the single-clock, single-edge, state acquisition verifies the performa

3 Set up the oscilloscope. If the oscilloscope was not configured for the previous test,then do the following steps.a Select Setup, then select Defaul

2 Set up the Format menu.a Press the Format key. Select State Acquisition Mode, then select Full Channel/4KMemory/100MHz.b Select the field to the ri

Connect the logic analyzer1 Using the 6-by-2 test connectors, connect the first combination of logic analyzerclock and data channels listed in one of

Connect the HP 1662C or HP 1663C Logic Analyzer to the Pulse Generator TestingCombinationConnect to HP 8133A Channel 2 OutputConnect to HP 8133A Chann

Table of Contents1 General InformationAccessories 1–2Specifications (logic analyzer) 1–3Specifications (oscilloscope) 1–4Specifications (pattern g

Verify the test signal1 Check the clock pulse width. Using the oscilloscope, verify that the clock pulsewidth is 3.500 ns, +0 ps or −100 ps.a Enable

3 Check the data pulse width. Using the oscilloscope, verify that the data pulse widthis 3.500 ns, +0 ps or −100 ps.aOn the Oscilloscope, select [Def

Check the setup/hold combination1 Select the logic analyzer setup/hold time.a In the logic analyzer Format menu, select Master Clock.b Select the Setu

2 Disable the pulse generator channel 1 COMP (with the LED off).3 Using the Delay mode of the pulse generator channel 1, position the pulsesaccording

4 Select the clock to be tested.a In the Master Clock menu, select the clock field to be tested, then select the clockedge as indicated in the table.

5 Note: This step is only done the first time through the test, to create a Compare file.For subsequent runs, go to step 6. Use the following to cre

10 Using the Delay mode of the pulse generator channel 1, position the pulsesaccording to the setup/hold combination selected, +0.0 ps or −100 ps.aOn

12 Press the blue shift key, then press the Run key. If two to four acquisitions areobtained without the "Stop Condition Satisfied" message

To test the multiple-clock, multiple-edge, state acquisition(logic analyzer)Testing the multiple-clock, multiple-edge, state acquisition verifies the

3 Set up the oscilloscope. If the oscilloscope was not configured for the previous test,then do the following steps.a Select Setup, then select Defau

To test the single-clock, single-edge, state acquisition (logic analyzer) 3–24Set up the equipment 3–24Set up the logic analyzer 3–25Connect the lo

2 Set up the Format menu.a Press the Format key. Select State Acquisition Mode, then select Full Channel/4KMemory/100MHz.b Select the field to the ri

Connect the logic analyzer1 Using the 6-by-2 test connectors, connect the first combination of logic analyzerclock and data channels listed in one of

Connect the HP 1662C/CS/CP or HP 1663C/CS/CP Logic Analyzer to the Pulse Generator Testing Combination Connect to HP 8133A Channel 2 OutputConnect to

Verify the test signal1 Check the clock pulse width. Using the oscilloscope, verify that the clock pulsewidth is 3.500 ns, +0 ps or −100 ps.a Enable

3 Check the data pulse width. Using the oscilloscope verify that the data pulse widthis 4.500 ns, +0 ps or −100 ps.a In the oscilloscope Timebase men

Check the setup/hold with single clock edges, multiple clocks1 Select the logic analyzer setup/hold time.a In the logic analyzer Format menu, select M

d Adjust the pulse generator channel 1 Delay until the pulses are aligned according thethe setup time of the setup/hold combination selected, +0.0 ps

55 If you have not already created a Compare file for the previous test (single-clock,single-edge state acquisition, page 32), use the following steps

9 Using the Delay mode of the pulse generator channel 1, position the pulsesaccording to setup time of the setup/hold combination selected, +0.0 ps or

11 Press the blue shift key, then press the Run key. If 2 - 4 acquisitions are obtainedwithout the "Stop Condition Satisfied" message appea

To test the voltage measurement accuracy (oscilloscope) 3–73Set up the equipment 3–73Set up the logic analyzer 3–74Connect the logic analyzer 3–75

To test the single-clock, multiple-edge, state acquisition(logic analyzer)Testing the single-clock, multiple-edge, state acquisition verifies the perf

3 Set up the oscilloscope. If the oscilloscope was not configured for the previous test,then do the following steps.a Select Setup, then select Defau

2 Set up the Format menu.a Press the Format key. Select State Acquisition Mode, then select Full Channel/4KMemory/100MHz.b Select the field to the ri

Connect the logic analyzer1 Using the 6-by-2 test connectors, connect the first combination of logic analyzerclock and data channels listed in one of

Connect the HP 1662C/CS/CP or HP 1663C/CS/CP Logic Analyzer to the Pulse Generator TestingCombinationConnect to HP 8133A Channel 2 OutputConnect to HP

Verify the test signal1 Check the clock period. Using the oscilloscope, verify that the master-to-masterclock time is 10.000 ns, +0 ps or -250 ps. a

2 Check the data pulse width. Using the oscilloscope, verify that the data pulse widthis 4.000 ns, +0 ps or −100 ps.a In the oscilloscope Timebase m

Check the setup/hold with single clock, multiple clock edges1 Select the logic analyzer setup/hold time.a In the logic analyzer Format menu, select Ma

d Adjust the pulse generator channel 2 Delay until the pulses are aligned according thethe setup time of the setup/hold combination selected, +0.0 ps

4 If you have not already created a Compare file for the previous test (single-clock,single-edge state acquisition, page 32), use the following steps

4 Calibrating and AdjustingLogic analyzer calibration 4–2To calibrate the oscilloscope 4–3Set up the equipment 4–3Load the Default Calibration Fact

7 Test the next setup/hold combination.a In the logic analyzer Format menu, select Master Clock.b Turn off and disconnect the clock just tested.c Repe

To test the time interval accuracy (logic analyzer)Testing the time interval accuracy does not check a specification, but does check thefollowing:• 12

3 Set up the function generator according to the following table.Function Generator SetupFreq: 40.000 00 MHzAmptd: 1.00 VModulation: OffSet up the log

2 Set up the Format menu.a Press the Format key. Select Timing Acquisition Mode, then select Conditional HaltChannel 500 MHz.b Select the field to th

4 Set up the Waveform menu.a Press the Waveform key.b Move the cursor to the sec/Div field, then use the RPG knob to dial in 100 ns.c Select the Marke

Connect the logic analyzer1 Using a 6-by-2 test connector, connect channel 0 of Pod 1 to the pulse generatorchannel 1 output.2 Using the SMA cable and

To test the CAL OUTPUT ports (oscilloscope)Testing the CAL OUTPUT ports does not check a specification, but does check thefollowing:• DC CAL OUTPUT vo

Set up the logic analyzer1 Set up the Calibration menu.a Press the Waveform key.b Press the Waveform key again. At the pop up, select Scope Calibrati

Verify the DC CAL OUTPUT port1 Using the BNC-to-banana adapter, connect the BNC cable between the multimeterand the oscilloscope DC CAL OUTPUT connect

Set up the logic analyzer1 Set up the Calibration menu.a Select the Procedure field, then select Osc Out.b Select the Signal field, then select Probe