11
Setup Instructions
1. Use an external RF signal generator and a 6 dB power splitter to send the
clock signal to both the N4962A serial BERT 12.5 GB/Sand the N4968A
clock and data demultiplexer 44 Gb/s.
2. Bypass the N4962A serial BERT 12.5 Gb/s internal clock path, and connect
the clock signal directly to the pattern generator section clock input TX CKI.
A level of +4 dBm at TX CKI should be sufficient. Also connect the N4968A
clock and data demultiplexer 44 Gb/s clock output directly to the error
detector section clock input RX CKI.
3. May have to increase the clock power to the N4962A serial BERT 12.5 Gb/s
pattern generator to get a clean, error free eye, but be careful not to exceed
the clock Input 1 level to the N4968A clock and data demultiplexer 44 Gb/s
which is about +4 dBm—may want to add an additional attenuator in line,
6 dB should be sufficient.
4. Data input signal to the N4968A clock and data demultiplexer 44 Gb/s must
be ac-coupled 1.0Vpp or swing about 0V. A dc block is recommended at the
input.
5. Terminate all unused inputs & outputs with 50 Ω loads.
6. Aligning the 14.2G clock and data. Once connected up, adjust the N4968A
clock and data demultiplexer 44 Gb/s phase shifter to align the clock and
data inputs to the 1:2 demux for error free operation. Do this by monitoring
the N4962A serial BERT 12.5 Gb/s BER error light, and also noting the time
position of the Data Out4 eye crossing on the scope.
NOTE: Make sure the N4962A serial BERT 12.5 Gb/s receiver is OFF at this stage, ignore any
BER reading on the display, monitor only the status of the error light. First adjust the N4968A
clock and data demultiplexer 44 Gb/s phase shifter until the N4962A serial BERT 12.5 Gb/s
error light changes from off to on; note the time position of the eye crossing on the scope. Then
move the phase shifter in the opposite direction until it the error light again changes from off to
on; note again the time position of the eye crossing on the scope. Then adjust the phase shifter
one more time to position the eye crossing midway between the two previously noted values.
The 14.2 GHz clock should now be optimally aligned with the 14.2 Gb/s data at the N4968A
clock and data demultiplexer 44 Gb/s 1:2 demux.
7. Aligning the 7.1G clock and data. Next optimize the clock and data phase at
the N4962A serial BERT 12.5 Gb/s error detector input by using the auto-
phase feature within the N4962A serial BERT 12.5 Gb/s
Ensure the Receiver►On is not selected (the error detector must be off
Press the Display►Scroll || button and select Ø
Press the Adjust►Config State + button to auto-select the detector phase
Observe the Error ε light (should remain off, indicating no errors detected)
8. For fine tuning reiterate steps 6 and 7.
9. Turn on the N4962A serial BERT 12.5 Gb/s receiver to perform a BER
measurement.
(214 paginas)
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