Agilent Technologies N4962A Guía de usuario descargar pdf (Pagina 6)

BER Tester with an External Full-Rate Clock for 0.5 to 12.5 Gb/s

Applications

The N4962A serial BERT 12.5 Gb/s can also be used for applications within a

full range of operating rates from 500 Mb/s to 12.5 Gb/s. This is accomplished

by applying an external clock signal to the BERT clock inputs, RX CKI and TX

CKI, as illustrated in Figure 7.

LF TrigO

HF TrigO

JitterI

EXT CKI

TX CKO

~IN

~OUT

OUT

RX CKI

RX CKO

TX CKI

N4962A serial BERT

12.5 Gb/s

DUT

Power

splitter

OUT, +10 dBm

clock

synthesizer

Figure 7. Block diagram – multi-rate BER

measurement of DUT with external clock

Because the BERT receiver has an internal electronic phase-adjuster, the

coaxial cables connecting the power splitter to the TX CKI and RX CKI inputs do

not need to be phase matched.

The clock input (TX CKI and RX CKI) power input requirements are typically

+4 dBm, so the synthesizer should generate more than a +7 dBm output if a

power splitter is used.

Consult the BERT Users’ Guide for detailed procedures regarding the use of

an external clock: change the synth option to 0, adjust the freq setting to the

approximate frequency rate.

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Agilent Technologies N4962A Guía de usuario Pagina 6