Agilent Technologies N4962A Guía de usuario descargar pdf (Pagina 5)

BER tester with an External Divider for Low-Rate Applications

The N4962A serial BERT 12.5 Gb/s can also be used for applications below the

internal clock range of 9.85 to 11.35 Gb/s, within the operating limits of

0.5 to 12.5 Gb/s. This is accomplished by using an external divider (Agilent

offers several programmable units) in the clock path, as illustrated in Figure 6.

LF TrigO

HF TrigO

JitterI

EXT CKI

TX CKO

~IN

~OUT

OUT

RX CKI

RX CKO

TX CKI

N4962A serial BERT

12.5 Gb/s

DUT

÷N÷N

Figure 6. Block diagram – BER measurement

of low operating rate differential DUT

The output from the BERT internal clock system (RX CKO and TX CKO) is GPIB

and front-panel programmable between 9.85 to 11.35 GHz. Using external divid-

ers, part number UXC20PE, the clock can be divided to a lower rate and the test

system can be used in the operating ranges listed in Table 1.

Because the BERT receiver has an internal electronic phase-adjuster, the coax

cables connecting the TX CKO and RX CKO to the dividers, and the dividers to

the TX CKI and RX CKI inputs, do not need to be phase matched.

Divider Divide ratio Operating range

None None 9.85 to 11.35

UXC20PE Divide-by-2 4.925 to 5.675

UXC20PE Divide-by-4 2.4625 to 2.8375

UXC20PE Divide-by-8 1.23125 to 1.41875

Table 1. BERT operating range with external programmable divider

Consult the BERT Users’ Guide for detailed procedures regarding the use of an

external clock: change the synth option to 0, then adjust the freq setting.

1 2 3 4 5 6 7 8 9 10 11 12

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Agilent Technologies N4962A Guía de usuario Pagina 5