Agilent Technologies 16800 Series Manual de usuario descargar pdf (Pagina 3)

Design step 1: Configure the logic

analyzer interface file and core

parameters

You need to create a logic

analyzer interface file with

the logic analyzer interface in

Quartus II. This file defines the

interface that builds a connection

between the internal FPGA

signals and the logic analyzer.

You can then configure the core

parameters, which include

number of pins, number of signal

banks, the type of measurement

(state or timing), clock and the

power-up state.

A quick tour of the application

Design step 2: Map the logic analyzer

interface core outputs to available

I/O pins

Use Pin Planner in Quartus II to

assign physical pin locations for

the logic analyzer interface core.

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Agilent Technologies 16800 Series Manual de usuario Pagina 3