4
A quick tour of the application (continued)
Design step 3: Assign logic analyzer
interface bank parameters
Assign internal signals to each
bank in the logic analyzer
interface after you have specified
the number of banks to use in the
core parameters. Find the signals
you want to acquire with the
Node Finder and assign them to
the banks.
With the logic analyzer interface
core fully configured and
instantiated into your FPGA
design, you’re ready to compile
your design to create the device
programming file (.sof). Then, to
make measurements you’ll move
to the Agilent logic analyzer
software.
Activate FPGA dynamic probe
for Altera
The FPGA dynamic probe icon
allows you to control the logic
analyzer interface and set up the
logic analyzer for the desired
measurements.
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