3
A quick tour of the application
Design step 1: Create the ATC2 core
Use Xilinx Core Inserter or EDK
to select your ATC2 parameters
and to create a debug core that
best matches your development
needs. Parameters include
number of pins, number of signal
banks, the type of measurement
(state or timing), and other ATC2
attributes.
Design step 2: Select groups of
signals to probe
Specify banks of internal signals
that are potential candidates for
logic analysis measurements
(using Xilinx Core Inserter
or EDK).
Activate FPGA Dynamic Probe
The FPGA dynamic probe icon
allows you to control the
ATC2 Core and setup the
logic analyzer.
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