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Agilent B4655A specifications and characteristics
Supported logic analyzers
Standalone logic analyzers 1680 Series, 1690 Series, 16800 Series
Modular logic analysis systems 16900A, 16902A, 16903A with one or more state/timing modules:
A single node-locked FPGA dynamic probe license will enable all
modules within a 16900 Series system
Triggering capabilities Determined by logic analyzer
Supported Xilinx FPGA families Virtex-5, Virtex-4, Virtex-II Pro series, Virtex-II series, Spartan-3 series
Supported Xilinx cables (required) Parallel 3 and 4, Platform Cable USB
Supported probing mechanisms Soft touch (34-channel and 17-channel), Mictor, Samtec, Flying lead
FPGA dynamic probe software application
Maximum number of devices supported on a JTAG scan chain 256
Maximum number of ATC2 cores supported per FPGA device 15
Agilent trace core characteristics
Number of output signals User definable: Clock line plus 4 to 128 signals in 1 signal increments
Signal banks User definable: 1, 2, 4, 8, 16, 32, or 64
Modes State (synchronous) or timing (asynchronous) mode
Compression Optional 2X compression in state mode via time division multiplexing.
Logic analyzer decompresses the data stream to allow for full
triggering and measurement capability.
FPGA Resource consumption Approximately 1 slice required per input signal to ATC2 Core
Consumes no BUFGs, DCM or Block RAM resources.
See resource calculator at www.agilent.com/find/fpga
Compatible design tools
ChipScope Pro Version 1680, 1690, 16800, 16900 Series SW Version Primary New Features
6.2i, 6.3i 2.5 or higher Mouse-click bank select, graphical pin mapping,
.cdc signal name import
6.2i, 6.3i 3.0 or higher Support for Virtex-4 devices, improved JTAG drivers,
single-session multi-core support, user-definable naming
7.1i 3.2 or higher Plug & run (auto pin mapping), ATC2 “always on” option,
ATC2 width + 64 banks, Platform Cable USB support,
PRBS stimulus on test bank
8.2i 3.5 or higher Support for Virtex-5, 16800 Series
EDK (Embedded Development Kit)
8.1i SP2 3.2 or higher Support for ATC2 core using EDK flow
Synthesis Core Inserter produces ATC2 cores post-synthesis (pre-place and
route) making the cores synthesis independent.
ATC2 cores produced by Core Generator are compatible with:
• Exemplar Leonardo Spectrum
• Synopsys Design Compiler
• Synopsys Design Compiler II
• Synopsys FPGA Express
• Synplicity Synplify
• Xilinx XST
Additional information available via the Internet (www.agilent.com/find/FPGA) and www.agilent.com/find/fpga_FAQ.
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