Table 7: Specifications for the 10 MHz reference output
Amplitude 1V into 50 Ω typical
Interface AC coupled,
50 Ω output impedance
Connector BNC, rear panel
Table 4: Specifications for delay control input
Range --100 ps to +100 ps
Sensitivity 400 ps/V typical
Linearity ± 5 % typical
Modulation 1 GHz typical at 10.8 Gb/s
bandwidth data rate
Levels --250 mV to +250 mV
Interface DC coupled, 50 Ω nominal
Connector SMA female
8 J-BERT N4903A High-Performance Serial BERT Data Sheet
Clock Output (CLK OUT)
Table 2: Clock output characteristics. All timing parameters
are measured at ECL levels
Frequency range 150 MHz to 12.5 GHz (opt. C13)
Can be programmed up to
13.5 GHz
150 MHz to 7 GHz (opt. C07)
<620 MHz only with external
clock
Amplitude/Resolution 0.1 V pp to 1.8 V pp, 5mV steps
Output voltage window --2.00 to + 2.8 V
Transition times
(20% to 80%) < 20 ps
(10% to 90%)
2)
< 25 ps
External termination --2 V to +3 V
voltage
3)
Jitter 1 ps rms typical with disabled
jitter sources
SSB phase noise < --75 dBc with internal
clock source. 10 GHz @ 10
kHz offset, 1 Hz bandwidth
Interface
1)
Differential or single-ended,
DC coupled, 50 Ω output
impedance
Connector 2.4 mm female
1)
Unused outputs must be terminated with 50 Ω to GND.
2)
At 10 Gb/s and 7 Gb/s
3)
For positive termination voltage or termination to GND, exter
nal termination voltage must be less than 3 V below VOH. For
negative termination voltage, external termination voltage
must be less than 2 V below VOH. External termination
voltage must be less than 3 V above VOL.
Table 3: Specifications for clock input and 10 MHz reference
input
Amplitude 200 mV to 2 V
Interface AC coupled, 50 Ω nominal
Connectors Clock input: SMA female,
front panel
10 MHz Reference Input:
BNC, rear panel
Table 5: Specifications for error inject input
Levels TTL compatible
Interface DC coupled, 50 Ω nominal
Connector SMA female
Table 6: Specifications for subrate clock output
Divider factors n = 2,3…128
Levels High: + 0.5 V
Low: --0.5 V typical
Transition times 35 ps typical
Interface DC coupled, 50 Ω, differential
or single-ended
Connector SMA female
Clock Input (CLK IN) and 10 MHz Reference Input
(10 MHZ REF IN)
Clock input: uses an external clock as generator clock.
10 MHz Reference input: If a 10 MHz reference clock is
applied, the internal PLL (used to generate the inter-
nal clock for the generator) is locked to the applied
signal.
Delay Control Input (DELAY CTRL IN)
The external signal applied to delay control input,
varies the delay between Data Output to Clock
Output. This can be used to generate jittered signals
to stress the device under test in addition to the
calibrated jitter infection from N4903A.
Error Add Input (ERROR ADD)
The external error add input adds a single error to
the data output for each rising edge at the input.
Subrate Clock Output (SUB CLK OUT)
The subrate clock output is used to generate refer-
ence clocks, which are subrates of the data rate, for
example, a 100 MHz clock for 2.5 or 5 Gb/s PCI
Express data rate.
10 MHz Reference Output (10 MHZ REF OUT)
(320 paginas)
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