J-BERT N4903A High-Performance Serial BERT Data Sheet 9
Table 8: Specifications for trigger output
Pulse width Square wave
Transition times 35 ps typical
Levels High: +0.5 V; Low -- 0.5 V typ
Interface DC coupled, 50 Ω nominal,
single ended or differential
Connector SMA female
Table 9: Specifications for auxiliary input
Levels TTL compatible
Interface DC coupled, 50 Ω nominal
Connector SMA female
Table 10: Spread spectrum clocking (SSC) characteristics
Frequency deviation 0 to --0.5%,
2% typical accuracy
Modulation Frequency 28 kHz to 34 kHz
Waveform Triangle
Signals impacted Subrate clock output,
data output, clock output,
trigger output
Patterns
PRBS: 2
n
-1 with n = 7, 10, 11, 15, 23, 31,
and 2
n
with n = 7, 10, 13, 15, 23, 31.
User-definable pattern: 32 Mbit, independent for pattern
generator and error detector.
Generator Pattern Sequencing
The generators pattern sequences can be started on
command or by a signal applied to the auxiliary
input.
Number of blocks: up to 4; the block resolution of user
definable pattern is 512 bits.
Loops: over 4 or fewer blocks. 1 loop level. Loop
counter and infinite .
Alternate Pattern
This allows switching between two patterns of equal
length that have been programmed by the user, each
of which can be up to 16 Mbit. Switching is possible
using a front panel key, over GPIB or by applying
the appropriate signal to the auxiliary input port.
Changeover occurs at the end of the pattern. The
length of the alternating patterns should be a multi-
ple of 512 bits. Two methods of controlling pattern
changeover are available: one-shot and alternate.
Zero substitution
Zeros can be substituted for data to extend the
longest run of zeros in the patterns listed below. The
longest run can be extended to the pattern length-1.
The bit following the substituted zeros is set to 1.
Variable mark density
The ratio of ones to total bits in the predefined pat-
terns listed below can be set to 1/8, 1/4, 1/2, 3/4, or
7/8.
Library of predefined patterns
SONET, SDH, FDDI, Fibre Channel, 10 GbE, K28.5
Trigger Outputs (TRIGGER OUT)
This provides a trigger signal synchronous with the
pattern, for use with an oscilloscope or other test
equipment. Typically there is a delay of 32 ns
between trigger and data output for data rates ≥
620 Mb/s. The trigger output has two modes.
Pattern trigger mode: for PRBS patterns; the pulse is
synchronized with a user specified trigger pattern.
One pulse is generated for every 4th PRBS pattern.
Divided clock mode: the trigger is a square wave with
the frequency of the clock rate divided by 2, 4, 8,
10, 16, 20, 32, 64, and 128.
AUX Input (AUX IN)
When the alternate pattern mode is activated, the
memory is split into two parts, and the user can
define a pattern for each part. Depending on the
operating mode of the auxiliary input, the user can
switch the active pattern in real-time by applying a
pulse (Mode 1) or a logical state (Mode 2) to the
auxiliary input. If the alternate pattern mode is not
activated, the user can suppress the data on the
data output by applying a logical high to the auxil-
iary input (Mode 3).
SSC – Spread Spectrum Clocking (option --J11)
The built-in SSC clock modulation source is available
only in combination with option J10.
It generates a frequency modulated clock signal as
used in some computer storage standards to spread
EMI. If spread spectrum clocking is enabled, sinu-
soidal jitter is disabled, however all other jitter
sources can be used.
Figure 14: Pattern generator sequencer helps to set up com-
plex training sequences
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