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Agilent N4903B J-BERT High-Performance Serial BERT
• Operates from 150 Mb/s to 7, 12.5 or 14.2 Gb/s
• Built-in calibrated and compliant jitter sources for RJ, PJ1, PJ2, SJ,
BUJ
•
Interference channel with sinusoidal interference and switchable ISI
traces
• Automated jitter tolerance, compliance curve and characterization
• Second output channel with independent PRBS and pattern memory
• Built-in tunable CDR
• Half-rate clock with variable duty cycle, sub-rate clock outputs
J-BERT N4903B high-performance serial BERT
Complete receiver jitter tolerance
J-BERT provides built-in and calibrated jitter sources for the most
accurate jitter tolerance testing of receivers used in many popular
multigigabit serial bus interfaces.
It is used by R&D and test engineers in the semiconductor, computer, and
communication industry to characterize new designs and verify standard
compliance.
J-BERT supports testing of embedded and forwarded clock architectures
for data rates up to 14.2 Gb/s.
Long-term investment
J-BERT is configurable for today’s test and budget needs but allows
retrofit of all options when test needs change.
Key applications
• Receiver jitter tolerance
• PCI Express, USB3, SATA, SAS, DisplayPort
• Forwarded clock interfaces: QPI
• Fibre Channel
• XFP, SFP, SFP+, 10 GbE, XAUI, 100 GbE (10 x 10 Gb/s)
• Backplanes: CEI, 10 GBASE-KR, 100 GBASE-KR4
Measurement suite
•
BER,accumulated,interval;symbol/frameerrorratio(OptionA02);bit
recoverymode(OptionA01);patterncapture
• BERT scan, “bathtub” curve including RJ, DJ, TJ separation
• Output level, Q-factor, eye-diagram with BER contour and eye masks
• Fast eye mask, spectral jitter, error location capture, fast TJ
Specifications
Pattern generator
• Operation range: 620 Mb/s
1
to 7 Gb/s (Option C07 or G07), to
12.5 Gb/s (Opt C13 or G13), to 14.2 Gb/s (Opt G13 + D14 or C13 +
D14)
• Data outputs: 1 or 2 (Option 002), differential or single-ended
• Output amplitude: 0.1 to 1.8 Vpp
• Jitter: < 9 ps pp
• Transition time: < 25 ps (10 to 90 % and ECL levels)
• Cross point adjust: 20 to 80 %
• Pattern: PRBS 2
n
– 1, n = 7, 10, 11, 15, 23, 31
• Memory: 32 Mbit and pattern sequencing (up to 120 blocks)
• Delay control input: Up to 220 ps for external jitter injection
•
1
150 Mb/s when using external clock source
Jitter tolerance test
• Built-in, calibrated jitter sources (Option J10): RJ up to 15.7 ps rms @
1 GHz, PJ1+2 up to 620 ps @ 300 MHz, SJ multiple UIs up to 5 MHz,
BUJ up to 220 ps, according CEI
• SSC (Option J11): Triangular and arbitrary modulation, up to
5000 ppm @ 0.1 to 100 kHz
• Interference channel (Option J20): ISI by switchable board traces,
sinusoidal interference (vertical eye closure) common and differential
mode up to 400 mV @ 3.2 GHz
Error detector
• Ext. Clock: 150 Mb/s to 7 Gb/s (Opt. C07) or 12.5 Gb/s (Opt. C13)
• Data input: 1, differential or single-ended
• Clock recovery: always incl., variable loop bandwidth 0.5 to 12 MHz
• Sensitivity: < 50 mV
Ordering information
• N4903B high-performance serial BERT with several accessories.
• N4903B-C07/C13 BERT with max. data rate 7/12.5 Gb/s
• N4903B-G07/G13 pattern generator w/ max. data rate 7/12.5 Gb/s
• N4903B-D14 data rate extension for pattern generator to 14.2 Gb/s
• N4903B-002 PRBS and pattern on aux data output (2
nd
output ch)
• N4903B-003 half-rate clock with variable duty cycle
• N4903B-J10 jitter sources (PJ1, PJ2, SJ, RJ, sRJ, BUJ)
• N4903B-J11 SSC, residual SSC
• N4903B-J12 jitter tolerance compliance suite
• N4903B-J20 interference channel
• N4903B-A01 bit recovery mode
• N4903B-A02 SER/FER analysis
• N4903B-UAB upgrade from N4903A
All options are upgradeable
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