Agilent Technologies J-BERT N4903B Manual de usuario

March 2011Francis Liu 劉宗琪Senior Project ManagerAgilent TechnologiesThe Latest Solution for Hi-Speed Serial Bus: PCI Express, SATA and USB Ver. 3.0 Te

S-ParametersS2P FileS21 Insertion Loss

{ 1,0,1} { 1,0,1} and 1n m n nnnTX PKc d cVV   1UI delay1UI delayC-1C0C1dm{-1,1}VTXTransmitter Equalization and Training-- Transmitter FIR

Coefficient Space and Presets Shown for the largest coefficient step size of 1/24 (smallest 1/63) Depending on coefficient resolution some quantizat

Electrical Validation of TransmittersPCIe Validation for PC devicesMotherboard TestingAdd-in Card TestingPCI-SIG AIC Test Fixture (CBB2)PCI-SIG System

Add-in Card (AIC) TX Testrx_spkgcbb_conn2RX SMPcbb_conn1TX SMPTest EquipmentAIC Under TestPost Processing S/WSigtest(Embed Channel + RX pkg + use beha

AIC RX Test Calibrationrx_spkgcbb_conn2RX SMPcbb_conn1TX SMPTest EquipmentCLB 3.0Post Processing S/W(Embed RX pkg + use behavioral EQ)Signal Generator

AIC RX Testrx_spkgcbb_conn2RX SMPcbb_conn1TX SMPError DetectorAIC Under TestSignal GeneratorSj + Rj + Diff Noise

PCIe 3.0 CBB FixtureLimited Detent SMPsSimilar to Gen2 CBBPrototypes in productionAvailability expected Feb-Mar 2

N5393C TX Test Application

Agenda Agilent position in various Hi-speed Digital Standards & Applications PCI Express 3.0 Spec Development and test solution Receiver Tolera

High-Speed Digital Markets & TechnologiesPCIe 3.0, SATA Gen 3 & USB 3.0: all above 5 Gb/sUSB 3.0QPIHT3MIPI100G EthernetSASDPSFP+8G5.4G14G4x25G

Key Challenges of PCIe 3.0 RX Test normative“ 8 GT/s over traditional FR4 PC-boards Requires post-processing of a step respo

PCIe 3.0 Receiver Test Challenges (Base Spec)2. How to sweep jitter amount over jitter modulation frequency?1. How to optimize pre- and post cursor de

• Built-in compliant & calibrated jitter injection• Automated jitter tolerance• Forwarded and embedded clocks• Characterization and complianceThe

Generating Pre-and Post-cursor De-emphasisDe-emphasis settings for PCIe 3.0 can be emulated by entering pre- and post-cursor values for N4916B direct

Stressed Jitter RX Test: setting RJ and SJ Straight forward and complete jitter set-up for both stressed jitter and stressed voltage eye testsFilteri

PCIe 3.0 Calibration ChannelsN4915A-014-25-20-15-10-501 1.5 2 2.5 3 3.5 4Breakout Channel OnlyBreakout + Short Calibration ChannelBreakout + Long Cal

PCIe 3.0 RX Test Stress Calibration ProcedureMeasure step response with RT Apply package model and RX CD,CTLE an

This Software automates PCIe 3.0 Stress Calibration and RX Test: N5990A-101 and -301Users can pick receiver tests and get results (green=pass). PCIe

PCIe 3.0 test Conclusions1. Probing at pins of device not practical at PCIe 3.0 speeds of 8GT/s.2. De-embedding may remove fixture effects and recover

Agenda Agilent position in various Hi-speed Digital Standards & Applications PCI Express 3.0 Spec Development and test solution Storage Total T

 Agilent position in various Hi-speed Digital Standards & Applications PCI Express 3.0 Spec Development and test solution Storage Total Test so

Transmitter Characterization(PHY/TSG/OOB)DSAX93204A oscilloscopeSATA, SAS compliance appN8801A Protocol viewer software*Receiver Characterization (RSG

Agilent Contributes to SATA-IO IW Program Certification of products for SATA-IO Integrators List There are currently 3 physical layer test areas at

SATA Approved Independent Test LabsAll SATA approved independent test labs use Agilent equipment for interoperability certification. Be confident with

T10 Committee SAS RoadmapSource: http://www.scsita.orgSAS 12Gbps is planned for the year 2010. The T10 committee is finalizing the SAS-2.1 spec, which

SAS 12G Scope Bandwidth RequirementThe calculation below assumes the data rate of SAS 12Gbps: 1UI = 83.33ps Rise Time (0.25 * 1UI) = 20.83ps Bandwi

True Analog Bandwidth + Low Noise Floor6 GHz1stharmonic18 GHz3rdharmonic30 GHz5thharmonicJBERT has fast edge, meaning lots of harmonic content.Notice

Gen3i CIC Definition for Jitter and AmplitudeThis could represent the 1-meter internal cable length.Before CICAfter CICTransmitterPage 36SATA / SAS Te

EQ+-Test FixtureTP0 TP1ScopeTxpTxnTxInfiniiSim for Embedding Gen3i CIC ChannelEmbed the Gen3i CIC channel and then make jitter and amplitude measureme

SATA Jitter DecompositionHow do I extrapolate jitter from Eye-diagram?TJDJRJPJISIDCDJitter DecompositionHow do you extrapolate TJ @ BER?TJBath Tub Cur

N5411B SATA Compliance Application N5411B 6Gb/s transmitter compliance application for scope and 81134A/N4903B pattern generator provides automated m

Agilent Digital Standards Program Leadership Ethernet compliance application  PCI EXPRESS compliance application  HDMI compliance application  SAS

SAS 12G Physical Layer Transmitter SolutionThe initial SAS 12G Transmitter solution will be available through User Defined Application (UDA) that can

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Agenda Agilent position in various Hi-speed Digital Standards & Applications PCI Express 3.0 Spec Development and test solution Storage Total T

SATA RSG - Receiver Jitter Tolerance TestMy RX Receives without ErrorJitter Tolerance Test = Verify How Good/Bad your Rx is.

SATA-IO RSG Compliance Test Spec Defined Jitter Values:TJ Gen1:501mUI Gen2:552mUI Gen3:570mUIFixed RJ(UI), SJ (UI), ISI (S-Para), Diff Vamp (mV)with

RSG-01/02/03/05/06 Receiver Test Setup Connection Diagram N4915A-005Switch1 12 2C CswitchPower DividerPower DividerProduct under testTxRxBIST L Source

ValiFrame N5990AOption 103, RSG and Receiver Characterization Tests  Automated Calibration Test Selection Test parameter Control(Expert Mode)  DUT

PHY-01 : Unit IntervalPHY-02 : Frequency Long Term StabilityPHY-03 : SSC Modulation FrequencyPHY-04 : SSC Modulation DeviationTSG-01 : Differential Ou

DisplayPort, USB 3.0, SATA, HDMI Compliance Tests Support

49Time Domain(For Gen1 device)Frequency Domain(For Gen1 to Gen3)SATA RXTX Measurement Example with the ENA Option TDRAll necessary parametersMeasured

Agenda Agilent position in various Hi-speed Digital Standards & Applications PCI Express 3.0 Spec Development and test solution Storage Total T

Infiniium 90000 Series Oscilloscopes And J-BERT B Provide Full Coverage For SATA PHY, TSG, OOB and RSGIncluding BIST commanding with true OOB signalin

Agenda Agilent position in various Hi-speed Digital Standards & Applications PCI Express 3.0 Spec Development and test solution Storage Total T

USB-IF Provides USB 3.0 Certification at Intel PILPIL is based at Intel OR, HillsboroAll Scope vendor solutions are being evaluated at the PILAgile

-or- -or-SuperSpeed Communication – Physical Layer FocusSuperSpeedNon-SuperSpeedSuperSpeedNon-SuperSpeedTXTXRXRXTXRXTX RXRXTXPoint to point communicat

-or-SuperSpeedNon-SuperSpeedRXTXTXRX-or-SuperSpeedNon-SuperSpeedTXRXTXRXUSB 3.0 SS Physical Layer Test SolutionsTrans-mitter(TX)Receiver(RX)Cable Agi

Page 55Transmitter test requirements(TX Far End)

Dec. 2008Compliance ChannelsCompliance Channels are used to test TX and RX for worst case channel conditionsBack panel USB route solutionChannel lo

U7243A USB 3.0 TX Compliance Application

Agilent SW embed vs Intel HW channel

Agenda Agilent position in various Hi-speed Digital Standards & Applications PCI Express 3.0 Spec Development and test solution Storage Total T

PCI-SIG PCI Express Standards OrganizationPCI Express Board of DirectorsAgilent, Intel, IBM, LSI Logic, Dell, HP, Sun Microsystems, nVidia, AMD PCI-SI

Page 60USB 3.0 Technical Review. 2009Turn on loopback by sending LFPS and required training sequencesThe receiver stress pattern is BDAT with SKPs ins

Dec. 2008Compliance ChannelsCompliance Channels are used to test TX and RX for worst case channel conditionsBack panel USB route solutionChannel lo

USB 3.0 Technical Review. 2009SuperSpeed Receiver Test Calibration and compliance channelsDevice compliance channel setupHost compliance channel setup

Page 63SuperSpeed Receiver Test Calibration and compliance channels

USB 3.0 PHY Rx Electrical Test Specification Key details to note in latest draft RX compliance calibration and testing performed at end of the chann

Cable and Connectors Compliance Time Domain Measurements Mated Connector Impedance Cable Electrical Performance  Characteristic Impedance  Intra-

DisplayPort, USB 3.0, SATA, HDMI Compliance Tests Support

Cable and Connectors Compliance- New Agilent E5071C Option TDRAll necessary parametersMeasured simultaneously Displayed in one screenFlexible measu

Summary Agilent is a key contributor in various technologies and standards over the years.  New test and interoperability challenges exist at 5Gb/s

PCI Express 3.0 Specification Changes New 12GHz oscilloscope maximum bandwidth specification De-embedding required (pin is reference for TX testing)

TX Measurement Challenges for PCIe 3.04.3.3.1.2. Measurement Setup for 8.0 GT/s Transmitters The PCIe electrical specification references all measure

Signal Path FlowEQ+-ConnectorTP0 TP1ChannelConnectorEQ+-TP2 TP3 TP4TxpTxn RxnRxpTx RxSignal generated hereExits IC hereExits board hereCombine measure