Agilent Technologies 8935 Series Especificaciones Pagina 304

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Chapter 10 303
Block Diagrams
CDMA Generator Section
Figure 10-13 CDMA Generator/Reference Assembly, A2A100
I_OFFSET
Q_OFFSET
QUADRATURE
REV
FWD
PARALLEL
TO
SERIAL
INTERFACE
POWER
SENSE/
REGULATOR
CLOCKS
+12AUX
+58UF
+50
PWR
+5
+15
-15
+5
+12
-12
-5V
POWER
SUPPLY
BUFFER
REF
SWITCHING
I/R
O
1/NF
O
I/R
1/NF
CH_B_DIAG
CDMA_TUNE
SYNTH_TUNE
LO/IF_DIAG
DIAG
MUX
DIVIDERS
8
8
3 dB3 dB
8
8
I_OUT (9.0)
Q_OUT (9.0)
MOD_DATA
CASS_STROBE
SER_DATA
SER_CLOCK
EVEN_SEC
19.6_CLK
ASIC
LOGIC
SYNC
CKT
D_RCV_DSP_TRIG
EVEN
SECOND/
SYNC IN
SIDE
PANEL
TO DATA
BUFFER
TRIGGER
QUALIFIER
IN
SERIALDATA
IN
NC
J3
SMB
SMB
SMB
SMB
J3
J2
REF_IN
10 MHz OUT
10 MHz REF OUT
10 MHz REF OUT
J3
2_SEC
80_MS
20_MS
26.67_MS
FRAME CLOCK OUT
SIDE PANEL
1.2288 MHz OUT
CHIP CLK
SIDE PANEL
10 MHz TO LO
10 MHz TO CDMA
CLOCK CKT
19.6608 MHz OUT
I
Q
SMB
TO IQ MODULATOR
QUAD
ADJ
SMBSMB
CDMA GENERATOR/REFERENCE ASSEMBLY, A2A100
TO DATA BUFFER
TO RECEIVE
DSP
10 PIN N.C.
4X CHIP TO
DSP
RECEIVE
MOTHERBOARD
TO DATA BUFFER
TO LO/IF
4X CHIP
16X CHIP CLOCK
DIAGNOSTIC MONITOR OUT
TO MEASUREMENT BOARD
TO KEYBOARD
REF CLOCK
MOTHERBOARD TO
REFERENCE
10 MHz
MOTHERBOARD
GATED BUS
REF OUT
EXT
REF IN
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