Agilent Technologies E1330B Manual de usuario Pagina 115
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Agilent E1330B Digital I/O Module Register Information 113
Appendix B
Port Transfer
Control Register
The Port Transfer Control Register controls transfers between the
mainframe and port, identifies port interrupts, and identifies forced
interrupts from the controller.
DRR (Data Register Ready) Is a read-only bit. When set to "1", it indicates either that the Port Data
Register contains valid data for the mainframe to read, or that the Port Data
Register is ready for the mainframe to write a byte of data to it. When the
Port Data Register is read, DRR is set to "0".
HE (Handshake Enable) When set to "1", enables handshaking for the port. You can read from or
write to this bit. When the registers have been initialized, you can set this bit
to "1" to enable handshaking if you are using the port handshake lines to
transfer data.
Bits 2 - 4 Are not used.
TI (Transfer Interrupt) Is a read-only bit. When set to "1", indicates a port transfer has occurred. A
port transfer interrupt, if enabled, occurs on a "port data register ready"
condition (when bit 0 of this register is set to "1"). To enable port transfer
interrupts, specify the "interrupt driven" transfer mode of port (refer to Port
Handshake Register) and set the "interrupt enable" bit (bit 7 of Interrupt
Control Register) equal to "1". When the Port Data Register is read, TI is set
to "0".
FI (Forced Interrupt) Is a read-only bit. When set to "1", indicates that a forced interrupt (from the
mainframe) has occurred. To force an interrupt, write a "1" to bit 6 and bit 7
of the Port Interrupt Control Register and bit 6 of the Status/Control
Register.
PI (Peripheral Interrupt) Bit 7 is a read/write bit. Writing a "1" to bit 7 enables port peripheral
interrupts. Writing a "0" disables port peripheral interrupts. When reading
bit 7, a "1" indicates a port interrupt has occurred. To clear PI you must write
a "0" to PI. Writing a "0" then a "1" to PI is the correct procedure to clear
one interrupt and re-enable for a second one.
Note Port peripheral interrupts are caused by a transition in the PIR line. If bit 4
of the Port Normalization Register is "0", a rising-edge (low to high)
transition caused the interrupt. If bit 4 is set to "1", a falling-edge (high to
low) transition caused the interrupt. Refer to the Port Normalization
Register for more information.
Port Address (0–3) base+0C
16
, base+0D
16
, base+0E
16
, base+0F
16
76543210
PI FI TI — — — HE DRR
- *E1330-90007* 1
- Contents 3
- 2 Contents 4
- Contents 3 5
- 4 Contents 6
- Certification 7
- Safety Symbols 8
- WARNINGS 8
- Documentation History 8
- DECLARATION OF CONFORMITY 9
- Getting Started 13
- 12 Getting Started 14
- Chapter 1 14
- Table 1-1. Data Lines 14
- Instrument Definition 15
- Downloading SCPI Drivers 15
- SCPI Command 16
- Format Used in This 16
- Specifying SCPI 16
- Commands 16
- Specifying Multiple Port 17
- Operations 17
- Initial Operation 18
- Chapter 2 19
- Using This Chapter 19
- Setting the Address Switch 20
- Enabling Pull-ups 21
- Selecting the Interrupt Line 22
- Combining the Flag Lines 23
- Using with External Pull-ups 30
- Typical Connection 31
- Chapter 3 33
- Addressing the Module 33
- Operation Overview 34
- Default and Reset States 35
- Setting the Polarity 35
- Setting the Handshake Mode 36
- Inputting Data Bytes and Bits 37
- Multiple Port Operations 39
- Using Trace Memory 40
- I/O Module 43
- The CTL Line 44
- Using the Handshake Modes 46
- Chapter 4 47
- 0 or 1. Byte or 53
- Multiple Port 56
- Input/Output 56
- Command Reference 59
- SCPI Command Reference 62
- DISPlay Subsystem 63
- :MONitor[:STATe]? 65
- MEASure Subsystem 66
- Parameters 67
- Comments 69
- MEMory Subsystem 70
- :VME:STATe 73
- • *RST Condition: Set to OFF 73
- :VME:STATe? 73
- [SOURce:] Subsystem 74
- 0.000002. MAX returns 0.015 81
- DIGital:DATAn[:type]:POLarity 84
- DIGital:DATAn[:type]:TRACe 85
- DIGital:FLAGn:POLarity 88
- DIGital:FLAGn:POLarity? 88
- DIGital:TRACe:DEFine? 94
- DIGital:TRACe:DELete:ALL 94
- DIGital:TRACe:DELete[:NAME] 94
- STATus Subsystem 95
- :OPERation:CONDition? 96
- :OPERation:ENABle 96
- :OPERation:ENABle? 96
- :OPERation[:EVENt]? 96
- :QUEStionable:CONDition? 97
- :QUEStionable:ENABle 97
- :QUEStionable:ENABle? 97
- :QUEStionable[:EVENt]? 97
- SYSTem Subsystem 98
- • Related Commands: *ERR 99
- • *RST Condition: None 99
- :VERSion? 99
- IEEE 488.2 Common Commands 100
- Command Quick Reference 101
- Chapter 5 104
- Appendix A 105
- Information 107
- A16 Address Space 108
- Outside the Command 108
- Module or Mainframe 109
- Inside the Command 109
- Reset and Registers 111
- Register Definitions 111
- Appendix B 112
- Register Descriptions 113
- Port Interrupt 114
- Control Register 114
- Port Transfer 115
- Port Control/ 116
- Status Register 116
- Port Handshake 118
- Register 118
- Table B-4. Handshake Type 119
- Table B-5. Range Multipliers 119
- Port Normalization 120
- Programming Examples 123
- Resetting the 124
- Reading the 125
- ID, Device 125
- Type, and 125
- Registers 125
- C Version 126
- Writing an 127
- 8-Bit Byte 127
- Writing a 129
- 16-Bit Word 129
- Reading an 130
- PIR Interrupts 133
- Agilent E1330 133
- B Non-data 138
- Line I/O 138
- Embedded 142
- Computer 142
- Error Messages 145
- 144 Error Messages 146
- Appendix C 146
- Agilent E1330B User’s Manual 147
- 146 Index 148
- C (continued) 149
- 148 Index 150
- I (continued) 151
- M (continued) 152
- P (continued) 153
- R (continued) 154
- S (continued) 155
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