Agilent Technologies J-BERT N4903B Manual de usuario descargar pdf (Pagina 14)

Sine wave

For all data rates

For data rates ≥ 8.1 Gb/s

Data rate (Gb/s)

12.5 Gb/s

2.5 Gb/s

2.75 UI

2.2 UI

1.1 UI

0.55 UI

5.0 Gb/s

10 Gb/s

Data rate x 220 ps

3000.001 20

100

1.0*

* 220 ps max.

Sine wave

triangular

square wave

Jitter

amplitude

(UI)

Modulation

frequency (MHz)

Jitter Tolerance Test Speciﬁcations

The built-in jitter sources are designed to cover DisplayPort,

PCI Express, SATA, USB3, Fibre Channel, QPI, Hypertransport,

FB-DIMM, CEI 6 G/11 G, 10 GbE and XFP/XFI, SFP+ jitter toler-

ance test needs.

Periodic jitter (Option J10)

This injects sinusoidal, rectangular

or triangular jitter over a wide

frequency range.

Table 11. Speciﬁcations for periodic jitter (PJ1, PJ2)

Range

0 to 220 ps pp at all data rates

0 to 610 ps pp at data rates

≤ 3.375 Gb/s

Modulation frequency

Sine

One- and two-tone possible

1 kHz to 300 MHz

Triangle/square 1 kHz to 20 MHz

Modulation frequency

accuracy

0.5% ± 25 Hz typical

Jitter amplitude accuracy 10% ± 1 ps typical

Impacted signals 610 ps delay line: only on data and aux

data outputs

220 ps delay line: user selectable for

data and aux data outputs, clock output

Jitter delay 0 to ±2.2 ns, 100 ps steps between

jitter on data and aux data output

versus jitter on clock output for all jitter

sources using the 220 ps delay line.

1. Available range depends on modulation frequency and data rate

(see Figures 18 and 19).

Figure 19. Periodic jitter maximum using the 220 ps delay line

Figure 18. Periodic jitter maximum for data rates ≤ 3.375 Gb/s using the

610 ps delay line

Jitter

amplitude

(UI)

Modulation

frequency

(MHz)

300

1.1*

Sine wave

Sine wave,

trinagular,

square wave

Data

rate x

610 ps

0.001

250

0.5*

* 610 ps max.

SSC – spread spectrum clocking (Option J11)

The built-in SSC clock modulation source is available only in combi-

nation with Option J10. It either generates a frequency modulated

clock signal (SSC) or a phase modulated clock signal (residual SSC)

as used in some computer or storage standards such as PCIe, USB

and SATA to spread EMI. If residual SSC is enabled, sinusoidal jitter

is not available, however all other jitter sources can be used. If SSC

is enabled, sinusoidal jitter is available in a limited range, however

all other jitter sources can be used without restrictions. SSC (% of

max) + SJ (% of max) ≤ 100%.

Table 12. Spread spectrum clocking (SSC) characteristics

SSC frequency deviation:

up-spread/down-spread

0 to -0.5% (5,000 ppm),

2% typical accuracy

SSC frequency deviation:

center-spread

0 to 1.0% pp (10,000 ppm),

2 % typical accuracy. Can be

used also for down-spread

SSC, allowing more SJ range

Residual SSC phase modulation 0 to 100 ps

Modulation frequency 100 Hz to 100 kHz

Modulation waveform Triangular or arbitrary.

Arbitrary files can be uploaded

as txt file. Values from -1.0 to

+1.0 for 1.0% center-spread

modulation, maximum of

16384 data points

Signals impacted Can be enabled for either data

and aux data output and/or

clock output and trigger/ref

clock out

1 2 ... 9 10 11 12 13 14 15 16 17 18 19 ... 25 26

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