Agilent Technologies J-BERT N4903B Manual de usuario descargar pdf (Pagina 18)

Error Detector Speciﬁcations

Data inputs (DATA IN)

Table 20. Speciﬁcations for error detector

Range of operation 150 Mb/s to 12.5 Gb/s (Option C13)

150 Mb/s to 7 Gb/s (Option C07)

Format NRZ

Max. input amplitude 2.0 V

Termination voltage

-2 V to +3 V or off

true differential mode

Sensitivity

< 50 mV pp

Intrinsic transition time

25 ps typical 20% to 80%, single ended

Decision threshold range -2 V to +3 V in 1 mV steps

Maximum levels -2.2 V to +3.2 V

Phase margin

1 UI – 12 ps typical

Clock-to-data

sampling delay

± 0.75 ns in 100 fs steps

Interface

Single-ended: 50  nominal,

differential: 100  nominal

Connector 2.4 mm female

1. Clock/data sampling delay range selectable 2 V operating voltage window,

which is in the range between

-2.0 V to +3.0 V. The data signals, termination voltage and decision threshold

have to be within this voltage window.

2. At 10 Gb/s, BER 10

-12

, PRBS 2

-1. For input levels < 100 mV manual threshold

value adjustments may be required.

3. At cable input, at ECL levels.

4. Based on the internal clock.

Error detector key characteristics:

• True differential inputs to match today’s ports

• Built-in CDR with tunable loop-bandwidth up to 12 MHz

• Auto-alignment of sampling point

• Bit recovery mode for unknown data traffic (Option AO1)

• SER/FER analysis of coded and retimed data (Option A02)

• Burst mode for testing recirculating loop

• BER result and measurement suite

• Quick eye diagram and mask with BER contours

Clock inputs (CLK IN)

The error detector requires an external clock signal to sample

data or it can recover the clock from the data signal using the

built-in clock data recovery (CDR).

Table 21. Speciﬁcation for the clock input

Frequency range 150 MHz to 12.5 GHz (Option C13);

150 MHz to 7 GHz (Option C07)

Amplitude 100 mV to 1.2 V

Sampling Positive or negative

clock edge

Interface AC coupled, 50  nominal

Connector SMA female

Clock data recovery

The error detector can recover the clock from the incoming data

stream with the built-in clock data recovery (CDR). The recovered

clock signal is available at the aux output.

Table 22. Speciﬁcations for the clock data recovery (Options C07, C13)

Input data rate 1 Gb/s to 12.5 Gb/s

(Option C13)

1 Gb/s to 7 Gb/s (Option C07)

CDR clock output jitter 0.01 UI rms (RJ) typical

Interface AC coupled, 50  nominal

Connector SMA female

1. With bit recovery mode (Option A01) enabled the max data rate is 11.5 Gb/s.

When using SER/FER analysis (Option A02), the max. data rate is 11.5 Gb/s.

Over-programming up to 12.5 Gb/s is possible, but SER/FER results are not

guaranteed.

2. When measured with PRBS 2

-1

Figure 25. Front panel connectors for error detection

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Agilent Technologies J-BERT N4903B Manual de usuario Pagina 18

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