Agilent Technologies J-BERT N4903B Manual de usuario descargar pdf (Pagina 21)

Auxiliary output (AUX OUT)

This output can be used to provide either clock or data signals:

Clock: clock signals from the input or the recovered clock signals

in CDR mode.

Data: weighted and sampled data.

Table 27. Speciﬁcations for the auxiliary output

Amplitude 600 mV typical

Interface AC coupled, 50  nominal

Connector SMA female

Gating input (GATE IN)

If a logical high is applied to the gating input the analyzer will

ignore the incoming bits during a BER measurement. The ignored

bit sequence is a multiple of 512 bits. For measuring data in bursts

of bits, rather than a continuous stream of bits, a special operating

mode is used. This is the burst sync mode. In this case, the signal

at the gating input controls the synchronization and the error

counting for each burst.

This is an important feature for recirculation loop measurements.

If clock data recovery (CDR) is used to recover the clock from the

burst data, the CDR takes 2 s from the start of the burst data to

settle. The number of bits needed to synchronize itself during a

burst depends on whether the pattern consists of hardware based

PRBS data or memory based data. To run properly in burst mode

the system needs a backlash of data after the gating input returns

to high. During each burst, the gating input has to remain passive.

Error Detector Speciﬁcations

Pattern capture

The error detector can capture up to 32 MB data bits from the

device under test. The captured data bits are displayed in the

pattern editor in hex or binary format. The data bits can be

used as expected data for BER testing or can be saved for post

processing.

SER/FER Analysis (Option A02)

The symbol error ratio (SER) analysis allows error counting of

coded, packetized and retimed data streams. SATA and USB3 are

popular examples of serial bus standards using retimed loopback

mode for receiver tolerance testing. SER analysis includes the

automatic handling of the running disparity of 8B/10B coded

patterns, filtering of up to 4 user-definable filler symbols, filtering

without any dead times up to 11.5 Gb/s (up to 12.5 Gb/s when

using analyzer with external clock) display of the error ratio as

SER or calculated BER. This requires SW rev. 6.6 or later. Frame

error ratio (FER) analysis requires SW rev. 6.8 or later. For PCIe

3.0 the option A02 enables the error counter to ignore changes

in length of 128 bit/130 bit coded Skip Ordered Sets. To use this

functionality N4903B software revision 7.40 or higher is required.

Analysis of 128b/132b coded patterns (Option A03)

The analysis of 128b/132b coded patterns enables receiver

testing of USB 3.1 ports. The BERT error detector ignores the

128b/132b coded Skip Ordered Sets during error counting. It is

able to handle the variable length of these SKP OS. The max. bit

rate for this mode is 10.35 Gb/s. To use option A03 functionality,

the N4903B software revision 7.60 or later is required.

Table 28. Speciﬁcations for gating input

Burst synchronization time 1536 bits for PRBS

15 kbit for pattern

Backlash 1536 bits in non-CDR mode

1.5 s in CDR-mode

Gate passive time

2560 bits in non-CDR mode

2560 bits or 1.5 s whichever

is longer, in CDR mode

Interface levels TTL levels

Pulse width 256 clock periods

Connector SMA female

Figure 28. Burst mode allows recirculation loop testing

Figure 29. The analyzer options A02 and A03 enable error counting of

devices such as PCIe, SATA, USB3.0 and USB3.1, that use retimed and

coded loopback.

Checked data

Backlash

CDR

settling

time

Sync. time

Burst

High

Low

Gate input

Data input

1 2 ... 16 17 18 19 20 21 22 23 24 25 26

Comentarios a estos manuales

Sin comentarios

Agilent Technologies J-BERT N4903B Manual de usuario Pagina 21

Comentarios a estos manuales

Relacionado con productos y manuales para Software Agilent Technologies J-BERT N4903B