
20
Error Detector Specifications
Trigger output (TRIG OUT)
Pattern trigger mode
This provides a trigger synchronized with the selected error
detector reference pattern. In pattern mode the pulse is synchro-
nized to repetitions of the output pattern. It generates 1 pulse for
every 4th PRBS pattern.
Divided clock mode
In divided clock mode, the trigger is a square wave.
Table 25. Specifications for trigger output
Clock divider 4, 8, 16 up to 11 Gb/s
32, 40, 64, 128 up to 12.5 Gb/s
Levels High: +0.5 V typical
Low: - 0.5 V typical
Minimum pulse width Pattern length x clock period/2
e.g. 10 Gb/s with 1000 bits = 50 ns
Interface DC coupled, 50 nominal
Connector SMA female
Error output (ERR OUT)
This provides a signal to indicate received errors. The output is
the logical ‘OR’ of errors in a 128 bit segment of the data.
Table 26. Specifications for error output
Interface format RZ, active high
Levels High: 1 V typical
Low: 0 V typical
Pulse width 128 clock periods
Interface DC coupled, 50 nominal
Connector SMA female
J-BERT measurements
• BER results
• Symbol error ratio (SER) and calculated BER (Option A02)
• Frame error rate (FER) analysis (Option A02)
• BER results with filtering of 8b/10b coded filler symbols or
128b/130b coded SKPOS symbols (Option A02)
• Accumulated BER results
◦ Accumulated errored O’s and 1’s
◦ G.821
◦ Error-free intervals
◦ Accumulated parameters
◦ Burst results
• Eye diagram results
◦ 1-/0- level
◦ Eye height/amplitude/width
◦ Jitter p-p and rms
◦ Cross-over voltage
◦ Signal to noise ratio
◦ Duty cycle distortion
◦ Extinction ratio
• Measurement suite
◦ BERT scan with RJ/DJ separation
◦ Spectral jitter decomposition
◦ Eye contour
◦ Quick eye diagram and BER contour
◦ Fast eye mask
◦ Output level and Q factor
◦ Error location capture
◦ Fast total jitter
• Pattern capture
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