Agilent Technologies E5071C Guía de usuario Pagina 520

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520 Appendix B
Status Reporting System
Status Register Structure
Issuing the *CLS command will clear all bits from the questionable bandwidth limit status
event register.
Issuing the *CLS command will clear all the bits in the questionable limit channel {1-4}
status event register.
Table B-6 Status Bit Definitions of the Questionable Limit Status Condition Register
Bit
Position
Name Description
0 Not used Always 0
1 Channel 1 Limit Test Fail (questionable
limit channel 1 status register summary)
Set to “1” while one of the enabled bits in the
questionable limit channel 1 status event register is
set to “1.”
2 Channel 2 Limit Test Fail (questionable
limit channel 2 status register summary)
Set to “1” while one of the enabled bits in the
questionable limit channel 2 status event register is
set to “1.”
3 Channel 3 Limit Test Fail (questionable
limit channel 3 status register summary)
Set to “1” while one of the enabled bits in the
questionable limit channel 3 status event register is
set to “1.”
4 Channel 4 Limit Test Fail (questionable
limit channel 4 status register summary)
Set to “1” while one of the enabled bits in the
questionable limit channel 4 status event register is
set to “1.”
5-15 Not used Always 0
Table B-7 Status Bit Definitions of the Questionable Limit Channel {1-4} Status Condition
Register
Bit
Position
Name Description
0 Not used Always 0
1 Trace 1 Limit Test Fail Set to “0” when a measurement cycle begins;
set to “1” when the measurement cycle finishes and
returns “fail” as the limit test result for trace 1.
2 Trace 2 Limit Test Fail Set to “0” when a measurement cycle begins;
set to “1” when the measurement cycle finishes and
returns “fail” as the limit test result for trace 2.
3 Trace 3 Limit Test Fail Set to “0” when a measurement cycle begins;
set to “1” when the measurement cycle finishes and
returns “fail” as the limit test result for trace 3.
4 Trace 4 Limit Test Fail Set to “0” when a measurement cycle begins;
set to “1” when the measurement cycle finishes and
returns “fail” as the limit test result for trace 4.
5-15 Not used Always 0
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