Agilent Technologies 8133A Manual de servicio Pagina 183

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Theory of Operation 8
16800 Series Portable Logic Analyzers Service Guide 183
Pattern Generation Block-Level Theory
Instruction Memory
The instruction memory holds the programmable vector flow
information and is paced in parallel with the data memory.
User- programmable instructions are stored in instruction
memory and control the pattern flow output.
Data Memory
Consisting of six 4Mx16 DRAM ICs and RAM addressing
circuitry, the data memory stores the desired pattern that
appears at the module output. The RAM addressing circuitry is
merely a counter which addresses the pattern locations in data
memory. When the end of the vector listing is reached, the
addressing circuitry is loaded from the loop register with the
address of the first vector of the listing to provide an
Figure 13 Pattern Generator Block Diagram
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