Agilent Technologies 8133A Manual de servicio descargar pdf (Pagina 91)

Troubleshooting 5

16800 Series Portable Logic Analyzers Service Guide 91

Analyzer Chip Memory Bus Test

The purpose of this test is to check the Analysis chip

memory busses that go between the Analysis chips and the

Memory Controller FPGAs.

System Clocks Test

The purpose of this test is to verify that the four clocks

(1/2/3/4) are functional between the master board and all

Analysis chips, and that the two Psync lines (A/B) are

functional between the master board's Analysis chips and all

Analysis chips in the module. This test verifies that the four

clock lines are driven from the master board and can be

received by all Analysis chips, and that the Psync lines can

be driven by each master chip on the master board and

received by all other Analysis chips in the module.

Turbo Clock Divider Test

The logic analyzer has a clock divider on the board, used for

single edge turbo state. This test verifies that the divider

routing works, and that it resets low.

System Backplane Clock Test

The purpose of this test is to verify the system backplane

100 MHz clock is functional to each Analysis chip and

running at the correct frequency. This test also verifies that

the PLL in each chip can be configured in bypass mode

(PLL is not used), then verifies that the PLL can be enabled

and used to generate additional clock frequencies.

Comparators Test

The purpose of this test is to verify that the front-end signal

comparators are able to be set to maximum and minimum

thresholds and that they are able to recognize activity on

each input using the cal input clock.

Inter-chip Resource Bus Test

The purpose of this test is to verify that the Inter- chip

Resource lines (ICRs) can be driven as outputs and received

as inputs by each chip in the module.

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Agilent Technologies 8133A Manual de servicio Pagina 91