Agilent Technologies ESG Guía de usuario descargar pdf (Pagina 39)

Chapter 1 23

Signal Generator Overview

Rear Panel Overview

11. EVENT 2 Connector

With Option 001 or 002 installed, this connector outputs a data enable signal for gating

external equipment. The output is applicable when the external data is clocked into internally

generated timeslots. Data is enabled when the signal is low. With Option 401 installed

(Option 401 requires Option 001 or 002 hardware), a marker is output on the EVENT 2

connector every 26.67 milliseconds, corresponding to the start of each short code.

With Option 001 or 002 installed, there is a marker on/off condition associated with each

waveform point. A marker (3.3 V CMOS high when positive polarity is selected; 3.3 V CMOS

low when negative polarity is selected) is output on the EVENT 2 connector whenever a

Marker 2 is turned on in the waveform. (Markers are automatically turned on whenever you

set them in a waveform segment. When you combine waveform segments that contain Marker

2 into a sequence, the markers are automatically turned off until you toggle them on in either

the Edit Selected Waveform Sequence menu or in the Build New Waveform Sequence menu.)

The damage levels are > +8 V and <

−4 V. This female BNC connector is provided only on

signal generators with Option 001 or 002. On signal generators with Option 1EM, this output

is changed from a BNC to an SMB connector. With Option 401 this connector is used for

system reset output.

12. PATT TRIG IN Connector

This input can accept either a TTL/CMOS low to TTL/CMOS high or TTL/CMOS high to

TTL/CMOS low edge trigger. The minimum trigger input pulse width, high or low, is 100 ns.

The damage levels are > +8 and <

−4 V. This female BNC connector is provided only on signal

generators with Option 001 or 002. If you configure your signal generator with Option 1EM,

this input is changed from a BNC to an SMB connector.

With Option 001 and 002 installed, the input to the PATT TRIG IN connector is used to

trigger the internal digital modulation pattern generator to start a single pattern output or to

stop and re-synchronize a pattern that is being continuously output. The trigger edge is

latched and then sampled by the falling edge of the internal data bit clock to synchronize the

trigger with the data bit clock timing. The minimum delay from the trigger edge to the first

bit of the frame is 1.5 to 2.5 bit clock periods.

With Option 001 or 002 installed, this connector is the source for the external trigger for all of

the ARB waveform generator triggers. With Option 401 this connector is used for system reset

trigger input.

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Agilent Technologies ESG Guía de usuario Pagina 39