
Chapter 15 445
W-CDMA Uplink Digital Modulation for Receiver Test
W-CDMA Uplink Concepts
DPCH Synchronization
Figure 15-64 illustrates the timing alignment for the DPCH channel. Delay time is defined by
the sum of T0 (1024 chips = the standard timing offset between downlink and uplink), timing
offset, and timeslot offset.
Figure 15-64 DPCH Synchronization - Frame Timing Alignment
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